1. Field of the Invention
The present invention relates generally to a semiconductor device and process and, more particularly, to a device and method for making a self-aligned select gate for a split-gate flash memory structure.
2. Description of the Related Art
Traditionally, flash memory cells consist of a floating storage gate (i.e., material which is not electrically connected to any terminal) interposed between a select gate and the area of the silicon substrate that is the channel of the memory cell transistor. Erasing, writing, or reading of such a cell involves injecting or removing electrons to or from the floating gate. Applying different combinations of voltages on its control gate, source, drain, and substrate controls this erasing, writing and reading of the cell. To enhance cell performance, split gates are sometimes used. In such a device, either different gates are used for the erasing/writing and reading operations, or these operations are performed using different regions of the same gate structure.
For a split-gate non-volatile memory (NVM) to operate properly, it is necessary for the select gate to at least cover the distance between the drain region (or source region) and the floating gate. If this distance is not constant, the length of the select gate must overcompensate for the variance in distance to ensure the split-gate NVM operates properly. A process for making a split-gate NVM design which does not maintain this distance constant is referred to as a non-self-aligned split-gate process because the alignment of the drain region and the floating gate must be taken into consideration when forming the select gate. Due to the overcompensation in the select gate length, a non-self-aligned split gate process deters cell size scaling. Moreover, cell characteristics, such as program efficiency and cell current, are severely affected by misalignment, which may occur in a non-self-aligned gate process. Another problem is that asymmetrical programming, resulting from misalignment of the select gate, may disturb the immunity margin due to a larger threshold leakage for a shorter select gate length.